1. Technical Field
This invention relates generally to the field of semiconductors, and more particularly, to manufacturing of integrated circuits using advanced optical lithography.
2. Related Art
During patterning of integrated circuits (ICs), an optical system (e.g. a scanner) is used to transfer a circuit design to a substrate through an optical radiation illumination system and projection system. Masks are typically used to define patterns on objects. For example, photomasks are used in photolithographic systems to define patterns on semiconductor wafers to manufacture ICs. Typically, the mask is placed between a light source and the object. The mask selectively blocks, transmits, or otherwise modifies light from the light source to define a pattern on the object. A mask pattern may refer to a pattern of all or a portion of the mask that defines the pattern on the object.
The capability of an optical lithography system is defined by its resolution (R), which is governed by the Rayleigh equation: R=k1*(λ/NA), where λ is the wavelength of the radiation used, NA is the numerical aperture (NA) of the project system used, and k1 is process dependent adjustment factor.
As IC design gets smaller and smaller, Moore's law requires R of the optical lithography system to be smaller too. This pushes k1 near its physical limit, i.e., low k1 lithography regime. In a low k1 lithography regime, it is common to optimize the illumination source shape and polarization state of the illumination source to maximize resolution of the optical lithography system, while exhausting the options to reduce λ or increase NA. This is an example of a resolution enhancement technique (RET).
Various RETs provide different illumination shapes, e.g., annular, dipole, cross-pole, quasar, as well as composite illumination sources developed by source optimization software. Also, different polarization states are used with these illumination sources, e.g., linear X-polarization, linear Y-polarization, X+Y polarization, TE (azimuthal) polarization, TM (radial) polarization, and so on. Both polarization and composite illumination sources (e.g., shape and position of illumination source element) are widely used in advanced optical lithography to improve lithography capability to resolve a particular IC design for a specific orientation. How to effectively combine them together to improve lithography capability at both X and Y orientations has become challenging. Ineffective use in one orientation (e.g., Y) could degrade the performance in the other direction (e.g., X). For example, single dipole X illumination can significantly improve the lithography capability for dense lines at Y orientation, and vice versa. If dipole X and dipole Y are combined together (i.e., cross pole), lithography capability for both directions is compromised. The same is true for the polarization state of each composite illumination element (e.g., transverse electric (TE), transverse magnetic (TM), LinearX, LinearY, etc.). Current art approaches fail to provide desired lithography capability for a full chip IC design.
Source mask optimization (SMO) and source mask polarization optimization (SMPO) are two current art approaches that attempt to address this need by using polarization and composite source for a specific IC design. However, SMO and SMPO solutions are prohibitively complicated and costly for actual implementation in a manufacturing setting. In some cases, SMO and SMPO techniques over consider too many factors to converge to a reasonable solution. Often, the expected performance improvement is not realized due to implementation complication.
Furthermore, each point or pixel source has its own illumination profile and polarization characteristics. However, in reality, it is almost impossible to implement. Also it is very time consuming and costly. It is not necessary to get a desirable result with such complicated implementation.
One area this has become evident is with advanced optical lithography for off-brick or off-contact patterns, e.g., for double or triple pattern processes. Current art approaches have difficulty imaging such patters with good image contrast and adequate process window (DOF) at the directions of both long and short dimensions, especially for asymmetrical patterns. Often, the failure at one side of an asymmetrical pattern kills the yield of the whole chip.
As such, current art approaches are inadequate for at least the reasons described above.